1. Field of the Invention
This invention relates in general to a pulse width distortion correction logic level converter, and more particularly to a converter that converts differential logic while preserving the pulse width of the original signal.
2. Description of Related Art
In the early 1980""s a new movement in computer architecture began with the development of reduced instruction set computers, commonly referred to as RISC machines. The overall design philosophy was to keep the computer hardware as simple as possible but extremely fast.
Because the RISC movement started during the advent of the silicon revolution, most RISC processors have been implemented in silicon using metal-oxide semiconductor field-effect devices, or MOSFETs for short. MOSFETs have been the predominant device in the industry due to their simple structure, low-cost fabrication and high integration levels. Although other technologies (most notably bipolar junction transistors, or BJTs) have better performance than MOSFETs, the development of complimentary MOS devices (CMOS) dramatically reduced circuit power consumption levels and provided a technological edge in terms of power vs. performance.
In recent years bipolar devices have been overlooked for use in nearly all processors, primarily due to the conventional premise that bipolar circuits have higher power consumption. Because static CMOS circuits do not provide a direct path between power and ground, power is dissipated primarily when the circuit is switching and results in a dependence between power dissipation and frequency. In contrast, current-mode bipolar circuits have a constant flow of current (and hence higher static power dissipation) but the power dissipation does not increase significantly with frequency. Therefore, bipolar circuits may run faster and consume less power than CMOS circuits.
Current mode logic (CML) bipolar circuit technology is implemented for a variety of reasons. Current mode logic is inherently fast due primarily to current-steering and the avoidance of transistor saturation, has relatively few components and is simple to design. One essential characteristic of a current mode logic circuit is the use of two related but varying voltages rather than one variable node and a fixed reference potential.
Current mode logic is referred to as a differential circuit and the signals are called differential signals. The ability to reject noise present on both inputs is called common-mode rejection and current mode logic is more suitable for a high-speed digital environment. Differential circuit technology has some other unique advantages over single-ended circuits such as the elimination of reference voltages and xe2x80x9cfreexe2x80x9d inversions for digital logic (just switch the input signals).
There are also some disadvantages to differential logic. Since both wires in a differential pair switch simultaneously, the change in potential is effectively twice the absolute voltage swing of the wires. Because each wire experiences an effective voltage swing of twice the actual change, the capacitive coupling between the wires is also doubled.
On the other hand, the capacitance of a single node is generally reduced because a ground plane of a semi-insulating substrate is typically further away. One solution is to route differential signals apart from each other to reduce the effective voltage swing, but this can present more serious problems with noise. Both wires in a differential pair should be routed side-by-side in order to ensure that any noise is injected onto both signals in a differential pair and is rejected due to the common mode rejection property of CML. If wires are routed separately, the injected noise may not be identical and may not be rejected from the circuit output.
Therefore, when logic families are combined, such as current mode logic with CMOS, this allows limited voltage swing differential inputs to produce a single-ended CMOS output. However, this high speed, low power general purpose differential to single-ended converter induces propagation delays in a circuit design.
For example, the leading and trailing edge delays within the CML to CMOS converter are not required to match creating the pulse width distortion in an output signal of the converter.
It can be seen then that there is a need for a pulse width distortion correction logic level converter.
Specifically, to a converter that converts a small swing differential logic signal into full swing complementary metal-oxide semiconductor signal while preserving the pulse width of the original signal.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a pulse width distortion correction logic level converter, and more particularly to a converter that converts a small swing differential logic signal into full swing complementary metal-oxide semiconductor (CMOS) signal while preserving the pulse width of the original signal.
The present invention solves the above-described problems by providing a circuit that determines the pulse width distortion between two CML to CMOS converters. Specifically, by matching a leading edge delay between two CML to CMOS converters as well as determining the difference between a set and a reset delay on a latch.
A system in accordance with the principles of the present invention includes converting signals from a source by receiving a differential input signal and converting the differential input signal to a single-ended signal having a same pulse width as the differential input signal.
Other embodiments of a system in accordance with the principles of the invention may include alternative or optional additional aspects. One such aspect of the present invention is that the receiving and converting further includes receiving the differential input signal at a first and second converters, wherein the first converter generates a first output signal and the second converter generates a second output signal, respectively. Also, a latching device to latching the first output signal of the first converter and the second output signal of the second converter to produce a full swing single-ended output signal having the same pulse width as the input differential signal.
Another aspect of the present invention is that the converting of the differential input signal further includes converting the differential input signal to the first converter having a polarity and converting the differential input signal to the second converter having a reversed polarity.
Another aspect of the present invention is that the latching of the first and second output signals further includes setting the latching device with an edge of the first output signal of the first converter and resetting the latching device with an edge of the second output signal of the second converter.
Another aspect of the present invention is that the latching of the edge of the first and second output signals generate a full swing single-ended output signal width that is not sensitive to an absolute delay through the first and second converters.
These and various other advantages and features of novelty which characterize the invention are pointed out with particularity in the claims annexed hereto and form a part hereof. However, for a better understanding of the invention, its advantages, and the objects obtained by its use, reference should be made to the drawings which form a further part hereof, and to accompanying descriptive matter, in which there are illustrated and described specific examples of an apparatus in accordance with the invention.